1. Field of the Invention
This invention relates to integrated circuit semiconductor devices and more particularly to memory devices.
2. Description of Related Art
In MOS silicon gate technology there are several ways of establishing connection between a doped polysilicon conductor layer and a doped silicon substrate which are separated by a gate oxide layer. One such form of contact is a "buried contact" which provides direct contact between the polysilicon conductor layer and the substrate through a window in the gate oxide formed where the buried contact is to be made. An ohmic contact between the doped polysilicon conductor layer and the substrate is made by diffusion from the doped polysilicon conductor layer (which is more heavily doped) of dopant into the substrate. Then an insulating film layer is formed covering the buried contact.
U.S. Pat. No. 5,451,534 shows the use of buried contacts in SRAM device integrated circuit designs. Lithography and etching are used to form openings in the gate oxide layer thereby defining the buried contact openings. Then doped polysilicon line patterns are formed over the device the openings.
FIG. 9 shows a prior art device 28' with a P- doped substrate 30 has been covered with a gate oxide layer 36 over which the doped polysilicon gate electrode 44' of an FET device 45 and a lower polysilicon layer 38 have been formed. The device 28' includes S/D regions 47/48 formed in the substrate 30. In addition, there is a buried contact BC1 region 42' formed in the substrate 30 comprising N+ doped source/drain regions 47/48. Drain region 48 is just to the left of BC1 region 42' but is separated therefrom by an undoped region 46 into which no ions have been implanted during the formation of a N+ doped S/D regions 47/48. The buried contact region 42 in substrate 30 to the right of the FET 45 has been formed by doping with N+ ions implanted therein. A second polysilicon layer (44', 44") was patterned to produce the gate electrode 44' and the interconnect 44" over the lower polysilicon layer 38 and the buried contact region 42'. Interconnect 44" reaches down through an opening through lower polysilicon layer 38 and gate oxide layer 36 into electrical and mechanical contact with buried contact region 42' and therethrough into electrical contact with the P- substrate 30. The undoped region 46 with its high electrical resistivity illustrates the problem of separation between the buried contact region 42' and the drain region 48 by an undoped region, which increases resistance therebetween resulting in large effective buried contact resistance.
FIG. 10 shows a modification of FIG. 9 in which the undoped region 46 has been replaced by a trench between the drain region 48 and the buried contact region 42'. This illustrates the problem of formation of a trench 56 between the buried contact region 42' and the drain 48 which arises with a conventional process during etching because the buried contact region 42' will be attacked easily during the process of etching during the polysilicon patterning step. This trench 56 will result in additional leakage if the trench 56 is too large.